A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

PROJECT TITLE :

A 0.1–6.0-GHz Dual-Path SDR Transmitter Supporting Intraband Carrier Aggregation in 65-nm CMOS

ABSTRACT:

A four.8-mm2 0.1-half-dozen.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A straightforward approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the ability-scalable and feedforward compensation techniques, the facility of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a coffee-power subpath to cooperatively cowl different standards over zero.1-half dozen.zero GHz with a lot of flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with potency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <;-50-dBc image rejection ratio and <;-40-dBc local oscillating signal leakage once the calibration. System verifications have demonstrated -thirty one/- 51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the most path and one.7percent error vector magnitude (EVM) at 1.5-dBm output for one.8-GHz WCDMA within the subpath. Both ways enable SAW-less FDD operations with -153 or -156 dBc/Hz carrier-to-noise ratio at two hundred-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and zero.eight%, respectively, and exhibiting the intraband CA capability.

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