Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote Allocation PROJECT TITLE :Comparator Power Reduction in Low-Frequency SAR ADC Using Optimized Vote AllocationABSTRACT:When operating at scaled provide voltages, the first source of performance degradation in a successive approximation register (SAR) analog-to-digital converter (ADC) is that the comparator thermal noise. Low-noise comparator will be used however at the expense of increased power dissipation. This paper presents an approach to reduce the comparator power in SAR ADCs. A mathematical model of a SAR ADC derived in this paper suggests that using the same comparator noise variance for every bit cycle is suboptimal and ends up in additional power consumption than necessary. A noise programmable comparator based mostly on majority vote technique is proposed to regulate the comparator noise performance at every bit step. As a signal of concept, a 10-bit SAR ADC that operates at 0.5-V offer voltage and supports a flexible differential input dynamic vary from zero.four to one V has been fabricated in 65-nm CMOS method. The prototype achieves an efficient variety of bits starting from 7.one to nine.1 bits and a figure of merit from three.three to six.eight fJ/conversion step while operating at 250 kS/s. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Some Features of the Overlapped Subarrays Built Up of Beam-Forming Matrices for Shaping Flat-Topped Radiation Patterns Internet of You: Data Big and Small [Guest editors' introduction]
