A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-Nodes PROJECT TITLE :A Low-Power Architecture for Punctured Compressed Sensing and Estimation in Wireless Sensor-NodesABSTRACT:In wireless sensor nodes with a good power budget, minimizing each the number of transmitted data and therefore the complexity of the algorithms used for data compression are elementary in achieving long battery life-time. Compressed Sensing (CS) has been proposed to process incoming samples and turn out a smaller amount of data sufficient to reconstruct the original signal. We show that the design implementing parallel projection-based CS can be reused to realize a linear estimator in a position to minimize the transmitted information when the primary interest is the acquisition of a scalar feature of the signal rather than its entire profile. Further, we tend to increase the energy-efficiency of the architecture by puncturing the sample stream that permits the duty-cycle of each the analog front-finish and also the analog-to-digital converter to be reduced. We tend to found that typical CS acquisition can be made more energy-efficient as it tolerates a sure amount of random puncturing, and conjointly that more substantial power savings can be achieved when estimation is that the target and undersampling is optimized by a suitable algorithm. In the latter case, the power consumption of all circuit blocks in the signal chain can be reduced by additional than one order of magnitude with respect to the quality solution that samples and transmits raw knowledge for off-board processing. The effectiveness of optimized undersampling is demonstrated in 2 case studies; 1st, the estimation of the amplitude of an electrical signal, and second, the estimation of the maximum solar radiation measured by a true-world sensor. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Mobility Investigations on Strained 30-nm High- $k$ Metal Gate MOSFETs by Geometrical Magnetoresistance Effect Low-power 850 nm optoelectronic integrated circuit receiver fabricated in 65 nm complementary metal–oxide semiconductor technology
