PROJECT TITLE :

A 10-Bit Low-Power High-Color-Depth Column Driver With Two-Stage Multi-Channel RDACs for Small-Format TFT-LCD Driver ICs

ABSTRACT:

This study proposes a 10-bit low-power high-color-depth LCD column driver IC with 2-stage multi-channel RDACs and switch resistance compensation. The design removes intermediate buffers from 2-stage RDACs and uses international reference buffers to isolate the worldwide resistor string and output channels. As a result of the world resistor string is isolated from output channels, the world resistor string will use a bigger resistance price to achieve lower power consumption. This study proposes a class-AB buffer for the worldwide reference buffers to atone for the errors caused by the voltage drop on switches connected in series with the channel resistor string. The channel resistor strings also reuse the output stage current of the world buffer to cut back power consumption. A prototype of a 200-channel column driver was fabricated using zero.18-$mu$m/0.thirty five- $mu$m CMOS technology with the worst DNL/INL being one.a pair of/1.one LSB. The proposed 10-bit DAC occupies solely 66% of the world of a standard 8-bit RDAC using the identical technology. The two hundred-channel column driver consumes a complete static current of solely 0.thirty eight mA.


Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here


PROJECT TITLE: Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 ABSTRACT: A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin
PROJECT TITLE :A Wide-Range, Low-Power, All-Digital Delay-Locked Loop With Cyclic Half-Delay-Line ArchitectureABSTRACT:A 3 MHz-to-1.eight GHz, 94 μW-to-nine.5 mW, all-digital delay-locked loop (ADDLL) using 65-nm CMOS technology
PROJECT TITLE :A 2.67 fJ/c.-s. 27.8 kS/s 0.35 V 10-bit successive approximation register analogue-to-digital converter in 65 nm complementary metal oxide semiconductorABSTRACT:A design of a 10-bit 27.8 kS/s zero.35 V ultra-low
PROJECT TITLE :Low-power, parasitic-insensitive interface circuit for capacitive microsensorsABSTRACT:Capacitive transduction is ubiquitously employed at macro- and particularly micro-scales because of their simple structure and
PROJECT TITLE: Low-power, high-speed dual modulus prescalers based on branch-merged true single-phase clocked scheme - 2015 ABSTRACT: A brand new style theme meant to boost the performance of true single-part clocked (TSPC) twin

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry