Bitplane Image Coding With Parallel Coefficient Processing

PROJECT TITLE :

Bitplane Image Coding With Parallel Coefficient Processing

ABSTRACT:

Image coding systems are historically tailored for multiple instruction, multiple knowledge (MIMD) computing. Generally, they partition the (transformed) image in codeblocks that may be coded within the cores of MIMD-based mostly processors. Every core executes a sequential flow of instructions to method the coefficients within the codeblock, independently and asynchronously from the others cores. Bitplane coding could be a common strategy to code such knowledge. Most of its mechanisms require sequential processing of the coefficients. The last years have seen the upraising of processing accelerators with enhanced computational performance and power potency whose architecture is especially based mostly on the only instruction, multiple knowledge (SIMD) principle. SIMD computing refers to the execution of the same instruction to multiple information in a very lockstep synchronous method. Unfortunately, current bitplane coding ways cannot totally profit from such processors due to inherently sequential coding task. This paper presents bitplane image coding with parallel coefficient (BPC-PaCo) processing, a coding methodology that can method many coefficients inside a codeblock in parallel and synchronously. To the present end, the scanning order, the context formation, the chance model, and therefore the arithmetic coder of the coding engine are re-formulated. The experimental results suggest that the penalization in coding performance of BPC-PaCo with respect to the traditional ways is sort of negligible.

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