Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 PROJECT TITLE : Exploiting Intracell Bit-Error Characteristics to Improve Min-Sum LDPC Decoding for MLC NAND Flash-Based Storage in Mobile Device - 2016 ABSTRACT: A multilevel per cell (MLC) technique significantly improves the storage density, however additionally poses serious knowledge integrity challenge for NAND flash memory. This consequently makes the low-density parity-check (LDPC) code and therefore the soft-decision memory sensing become indispensable in the subsequent-generation flash-based solid-state storage devices. But, the utilization of LDPC codes inevitably increases memory read latency and, hence, degrades speed performance. Motivated by the observation of intracell unbalanced bit error likelihood and knowledge dependence in the MLC NAND flash memory, this paper proposes 2 techniques, i.e., intracell knowledge placement interleaving and intracell information dependence aware LDPC decoding, to efficiently improve the LDPC decoding throughput and energy efficiency for the MLC NAND flash-based mostly storage in an exceedingly mobile device. Experimental results show that, by exploiting the intracell bit-error characteristics, the proposed techniques along can improve the LDPC decoding throughput by up to eighty four.half dozenp.c and scale back the energy consumption by up to 33.a pair ofpercent whereas solely incurring less than zero.a pair ofpercent silicon space overhead. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest Logic Gates Low-Power Electronics Error Statistics Flash Memories Parity Check Codes Mobile Radio Bit-Error Characteristic Low-Density Parity-Check (LDPC) Codes Multilevel Per Cell (MLC) Nand Flash Solid-State Storage High-Performance NB-LDPC Decoder With Reduction of Message Exchange - 2016 Unequal-Error-Protection Error Correction Codes for the Embedded Memories in Digital Signal Processors - 2016