A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015 PROJECT TITLE: A High Speed 256-Bit Carry Look Ahead Adder Design Using 22nm Strained Silicon Technology - 2015 ABSTRACT:Using 22nm strained silicon technology, a high-speed 256-bit carry look ahead adder was designed during this project. The suggested adder combines the advantage of static and dynamic styles, each with lower leakage, greater immunity to noise and high velocity. By calculating the even and thus the odd carries separately using 2 separate Manchester carry chains, the speed performance of the proposed 256-bit adder is significantly improved. In HSPICE, the circuit is simulated with a VDD = 0.8V supply voltage within the high-performance 22nm PTM strained silicon CMOS technology. The results of the simulation show that the proposed 256-bit adder implemented using 8-bit adder modules shows a significant improvement in operating speed compared to the conventional 256-bit adder based primarily on quality four-bit MCC adder modules. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist - 2015 A Highly-Scalable Analog Equalizer Using a Tunable and Current-Reusable Active Inductor for 10-Gb/s I/O Links - 2015
