A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016 PROJECT TITLE: A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016 ABSTRACT: Transpose type finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that ends up in vital saving of computation. However, transpose form configuration does not directly support the block processing in contrast to direct-type configuration. During this project, we tend to explore the chance of realization of block FIR filter in transpose kind configuration for space-delay efficient realization of huge order FIR filters for each fastened and reconfigurable applications. Primarily based on a detailed computational analysis of transpose form configuration of FIR filter, we have a tendency to have derived a flow graph for transpose kind block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose type FIR filter. We tend to have derived a general multiplier-based mostly architecture for the proposed transpose type block filter for reconfigurable applications. A coffee-complexity style using the MCM scheme is additionally presented for the block implementation of fastened FIR filters. The proposed structure involves significantly less area-delay product (ADP) and fewer energy per sample (EPS) than the prevailing block implementation of direct-type structure for medium or giant filter lengths, whereas for the short-length filters, the block implementation of direct-type FIR structure has less ADP and fewer EPS than the proposed structure. Application-specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42percent less ADP and 40% less EPS than the simplest out there FIR filter structure proposed for reconfigurable applications. For the identical filter length and the same block size, the proposed structure involves 13p.c less ADP and twelve.eightp.c less EPS than that of the present direct-form block FIR structure. Did you like this research project? To get this research project Guidelines, Training and Code... Click Here facebook twitter google+ linkedin stumble pinterest An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC - 2015 A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT - 2015