Coding for Improved Throughput Performance in Network Switches - 2017

PROJECT TITLE :

Coding for Improved Throughput Performance in Network Switches - 2017

ABSTRACT:

Network switches and routers need to serve packet writes and reads at rates that challenge the foremost advanced memory technologies. As a result, scaling the switching rates is usually done by parallelizing the packet I/Os using multiple memory units. For improved browse rates, packets will be coded upon write, thus giving a lot of flexibility at read time to achieve higher utilization of the memory units. This paper presents a detailed study of coded network switches, and in particular, how to design them to maximise the throughput benefits over commonplace uncoded switches. Toward that objective, the paper contributes a selection of algorithmic and analytical tools to boost and evaluate the throughput performance. The foremost attention-grabbing finding of this paper is that the placement of packets within the switch memory is the key to each high performance and algorithmic efficiency. One explicit placement policy we decision “style placement” is shown to relish the most effective combination of throughput performance and implementation feasibility.

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