Synthesis for Width Minimization in the Single-Electron Transistor Array

PROJECT TITLE :

Synthesis for Width Minimization in the Single-Electron Transistor Array

ABSTRACT:

Power consumption has become one of the first challenges to meetMoore’s law. For reducing power consumption, single-electron transistor (SET) at room temperature has been demonstrated as a promising device for extending Moore’s law thanks to its ultralow power consumption in operation. Previous works have proposed automated mapping approaches for SET arrays that focused on minimizing the quantity of hexagons in the SET arrays. But, the world of an SET array is the product of the bounded height and also the bounded width, and the peak usually equals the amount of inputs in the Boolean function. Consequently, in this paper, we tend to specialize in the width minimization to reduce the space within the mapping of the SET arrays. Our approach consists of techniques of product term minimization, branch-then-share (BTS)-aware variable reordering, SET array design relaxation, and BTS-aware product term reordering. The experimental results on a collection of MCNC and IWLS 2005 benchmarks show that the proposed approach saves forty five% of width compared with the work by Chiang et al., which targeted on hexagon count minimization, and additionally saves 13% of width compared with the work by Chen et al., which targeted on width minimization.

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