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PROJECT TITLE :

Modeling and Layout Optimization for Tapered TSVs

ABSTRACT:

Through-silicon-via (TSV) offers vertical connections for three-D ICs. Due to its massive dimensions and nonideal etching method, TSVs layout needs to be fastidiously optimized to balance peak current density and delay for digital circuit. This brief investigates the TSVs tapering result (that is an inevitable byproduct of deep reactive Ion etching-based manufacturing) and its impact on the TSVs electrical properties. We have a tendency to show that the present crowding impact is a lot of severe in realistic tapered TSVs than ideal cylindrical TSVs. We tend to propose a nonuniform current density model for tapered TSVs, that achieves considerable accuracy and speedup in estimating this density distribution, compared with the present models developed for cylindrical TSVs. We tend to apply our model to perform a detailed study on: 1) impact of TSVs tapering on peak current density and 2) wire sizing drawback to attenuate TSV-concerned path delay under second-order delay model whereas keeping the height current density at intervals tolerable levels. A brand new dynamic programming-primarily based heuristic is proposed to seek out the optimal wire configuration, which reduces both peak current density and delay, thereby improving the reliability and performance.


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