Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction

PROJECT TITLE :

Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction

ABSTRACT:

Scan tree architecture has been proposed to cut back the check application time of full scan chain by putting multiple scan cells in parallel. Most existing techniques depend on non-compact test pattern sets to construct the scan tree. But, they manufacture inefficient scan tree when highly compact test sets with few don't cares are used. In this paper, the depth of the scan tree based mostly on approximate compatibility relation for fully specified take a look at information set is analyzed probabilistically by modeling its construction as a vertex coloring problem. The higher sure of edges-per-vertex is computed and demonstrated to be a chief issue that limits the potency of scan tree construction primarily based on both compatible and approximately compatible test information between two flip-flops. Inverse compatibility and aggressive approximate compatibility are then proposed to extend the perimeters-per-vertex for vertex coloring. The Q′-SD connection between two adjacent scan cells is exploited to implement the inverse compatibility with no value or timing impact. To take care of the fault coverage, the missing faults beneath the tree scan mode can be detected by switching the same base design into the linear scan mode with negligible hardware overhead as shown by the experimental results on ISCAS89, ISCAS99 and LGSynth93 benchmark circuits. On average, the scan tree generated by our method reduces the check time of the total scan chain by fifty six.65 p.c, which of the scan tree designed by the approximate compatibility method by 39.18 % beneath the identical compact take a look at sets.

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