Repairing a 3-D Die-Stack Using Available Programmable Logic

PROJECT TITLE :

Repairing a 3-D Die-Stack Using Available Programmable Logic

ABSTRACT:

three-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are resulting in yield issues and slowing the large scale producing of these devices. In many cases, one defective die can kill the whole stack. To assist mitigate this issue, we tend to explore the chance of repairing a stack that contains a defective die by utilizing an field programmable gate array (FPGA) that has already been included in the stack for different purposes, like performance enhancement. Specifically, we propose bypassing the defective portion of a nonprogrammable die by replacing the defective functionality with functionality on the FPGA. In this paper, we have a tendency to discuss what extra logic must be added to an Application-Specific Integrated Circuit (ASIC) die to allow such a bypass to occur. We have a tendency to then show through detailed simulation of a 2.5-D Xilinx FPGA how bypassing of logic can be achieved and throughput maintained even when the 2 different dies involved operate at completely different frequencies. Finally, we explore the performance of this method in a very superscalar, out-of-order processor, where different functional units are marked for replacement. Our simulation results show that not only will we tend to salvage a device that will otherwise need to be discarded, however making multiple copies of the defective partition within the FPGA can allow us to regain performance even when the latency of the units in the FPGA is longer than that of the original defective copy.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here