( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2] - 2015

PROJECT TITLE:

( 4+2 log n ) Delta-G Modulo-(2^ Parallel Prefix n-3) Adder via Double Representation of Residues in [0,2] - 2015

ABSTRACT:

The most popular modulus in residue number systems (RNS), next to power-of-two modulus, are those of the form ( ). However, in RNS applications that require larger dynamic range, without increasing the parameter, modulus of the form ( ) are gaining popularity. Nevertheless, latencybalanced computational channels in RNS arithmetic systems are desirable. Ripple-carry modulo-( ) adders are realized simply as one’s complement adders, where serves as a second representation for 0. However, the same single -bit adder realization is not possible for modulo ( ). Given that efficient parallel prefix realization of modulo-( ) adders exist whose latency is compatible with similar modulo- adders, we are motivated to design latency compatible parallel prefix modulo-( ) adders. In this paper, we propose the fastest of such adders, where residues in ,, can be represented also as excess-( ) encoding (i.e., , , , respectively). The delay and area overhead of the proposed adder with respect to the base modulo-( ) adder, is only one extra gate in the critical delay path, and at most 20% more area. In very rare cases that both operands are excess-( ), augmenting the proposed adder with few extra gates leads to correct sum. The analytical results are confirmed by synthesis via Synopsys Design Compiler.

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