PROJECT TITLE :

An Efficient Decoder Architecture for Non-binary LDPC Codes with Extended Min-Sum Algorithm - 2016

ABSTRACT:

Nonbinary low-density-parity-check (NB-LDPC) codes, an extension of binary LDPC codes, offer stronger error-correcting capability than binary LDPC codes. However, the performance gain comes together with extraordinary increase on decoding complexity and memory requirement. Many simplification algorithms are proposed within the literature, and the extended min-sum (EMS) algorithm is that the one with minimal performance loss. During this brief, we gift an efficient decoder design for quasi-cyclic NB-LDPC codes with the EMS algorithm. The throughput is improved by not only the double-throughput elementary check node unit but conjointly overlapped processing for both check node and variable node units (VNUs). To reduce memory usage and computing complexity, edge-message hiding and simplified VNU are proposed yet. With these schemes, the postlayout results of a decoder for a (112, fifty six) NB-LDPC over GF(64) are presented. The core area occupies a pair of.24 mm2 and consumes 274 mW with a throughput of 124.6 Mb/s. Compared to prior NB-LDPC decoders with a similar code rate, the proposed decoder achieves better hardware potency and energy potency.


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Computational Complexity Decoding Parity Check Codes Cyclic Codes Decoding Scheduling Extended Min-Sum (EMS) Algorithm Nonbinary Low-Density-Parity-Check (NB-LDPC) Codes Very Large Scale Integration (VLSI)
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