A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

PROJECT TITLE :

A Double-Sensing-Margin Offset-Canceling Dual-Stage Sensing Circuit for Resistive Nonvolatile Memory

ABSTRACT:

Resistive nonvolatile memory (NVM) devices such as spin transfer torque random access memory (STT-RAM) and resistive random access memory are considered to be leading candidates for next-generation memory devices. With technology scaling, the sensing margin (SM) of the resistive NVM devices is significantly degraded as a result of of increased process variation and decreased scan current. In this transient, we propose an offset-canceling twin-stage sensing circuit (OCDS-SC) that has the two major blessings of offset voltage cancelation and double SM. Monte Carlo HSPICE simulation results using a 45-nm technology for STT-RAM show that the OCDS-SC achieves a scan access yield of 99.93% for 32 Mb (half-dozen.6 sigma) with a browse current of 15 $mumboxA$ and sensing time of 3.4 ns.

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