Design of Stochastic Computing Circuits Using Nanomagnetic Logic


We think about the planning of stochastic computing (SC) hardware based on spintronic devices. SC offers low-value implementations of arithmetic operations and high degrees of error tolerance. Compared to charge-primarily based devices, spin-based mostly devices might be lower energy, nonvolatile, etc. However, spin-based mostly devices can be essentially a lot of error prone than charge-based mostly devices. The wedding of SC architectures and spin-based devices has the potential to supply info processing systems that are strong, low energy, and nonvolatile. During this paper, we have a tendency to investigate SC hardware comprised of nanomagnetic logic (NML) devices. NML could be a “beyond-CMOS” technology that uses bistable magnets to store, method, and move binary information. We introduce new NML circuit structures that exploit distinctive features of the technology to efficiently understand hardware parts needed for an SC system (e.g., random number generation). We conjointly benchmark NML-primarily based SC circuits against other implementations, and illustrate how features that are distinctive to NML (e.g., inherent pipelining) will cause improved performance. Our results indicate NML SC implementations achieve smaller area footprints with reduced energy and delay when put next to CMOS equivalents.

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