Charged Device Model Reliability of Three-Dimensional Integrated Circuits


The interdie signal interfaces in a very 3-dimensional (three-D) integrated circuit are vulnerable to overvoltage stress induced by charged device model (CDM) ESD, although they do not essentially lie on any of the most ESD current ways. Circuit simulation shows that the magnitude of the strain is highly sensitive to the look of the ground distribution network on each the die and package levels. The placement of TSVs additionally impacts the stress generated at the interdie interfaces. If excessive, the voltage stress can be mitigated by putting a little ESD clamp at the interdie signal interface. A power offer domain might span multiple dies in a 3-D stack; this work investigates whether it is possible to get rid of the clamps from a number of the dies within the stack to save lots of silicon area without severely impacting the CDM reliability of the interdie interface circuits.

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