Towards Power Optimization and Implementation of Probabilistic Circuits Using Single-Electron Technology


With continuous CMOS technology scaling toward its physical limits, there has been a growing demand for next-generation technologies with nanometer scale and novel style architectures. Single-electron (SE) technology is one of these candidates that may lead to high density and low power consumption for large-scale integration, at a cost of reduced reliability. Considering the fact that probabilistic circuits are ready to comprehend fault-tolerant architectures, implementing probabilistic circuits with SE technology would be a natural answer for future electronic applications. In this paper, we tend to initial study the probabilistic behavior and implementation of SE logic, and show an exponential relation between logic gate's reliability and its energy consumption. A gate-level power optimization for probabilistic circuits is then proposed to attenuate their power price under given reliability constraints. Comparison with simulated annealing (SA) primarily based method shows that the proposed approach can obtain promising results among a reasonably short time.

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