Integrated Fault Location and Power-Quality Analysis in Electric Power Distribution Systems


This paper presents a strategy for automated disturbance analysis and fault location on electrical power distribution systems using a combination of contemporary techniques for network analysis, signal processing, and intelligent systems. New algorithms to detect, classify, and find power-quality disturbances are developed. The continuous process of detecting these disturbances is accomplished through statistical analysis and multilevel signal analysis within the wavelet domain. The behavioral indices of the present and voltage signals are extracted by employing the discrete wavelet remodel, multiresolution analysis, and the concept of signal energy. These indices are employed by a variety of independent Fuzzy-ARTMAP neural networks, that aim to classify the fault type and the facility-quality events. The fault location is performed when the classification method. A real life 3-part distribution system with 134 nodes-13.eight kV and 7.065 MVA-was used to check the proposed algorithms, providing satisfactory results, attesting that the proposed algorithms are economical, quick, and, on top of all, intelligent.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

PROJECT TITLE :Cost-Optimal Caching for D2D Networks With User Mobility: Modeling, Analysis, and Computational Approaches - 2018ABSTRACT:Caching well-liked files at the user equipments (UEs) provides an efficient way to alleviate
PROJECT TITLE :Design, Analysis, and Implementation of ARPKI: An Attack-Resilient Public-Key Infrastructure - 2018ABSTRACT:This Transport Layer Security (TLS) Public-Key Infrastructure (PKI) is based on a weakest-link security
PROJECT TITLE :SERvICE: A Software Defined Framework for Integrated Space-Terrestrial Satellite Communication - 2018ABSTRACT:The existing satellite communication systems suffer from ancient design, such as slow configuration,
PROJECT TITLE :A High Performance Gated Voltage Level Translator with Integrated Multiplexer - 2018ABSTRACT:Multiple offer voltages are commonly employed in designs to enable higher power performance through dedicated management
PROJECT TITLE :A Scalable Network-on-Chip Microprocessor With 2.5D Integrated Memory and Accelerator - 2017ABSTRACT:This paper presents a two.5D integrated microprocessor die, memory die, and accelerator die with two.5D silicon

Ready to Complete Your Academic MTech Project Work In Affordable Price ?

Project Enquiry