PROJECT TITLE :
A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS
This paper presents an influence- and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, like OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continual-time linear equalizer, variable gain amplifier, and a fourteen-tap call feedback equalizer, as well as eight floating taps. The transmitter features a a pair of:1 multiplexer with a duty cycle distortion corrected [*fr1]-rate clock and a full-rate supply-series terminated driver with a 5-faucet feed-forward equalizer. The shared PLL employs a transformer-primarily based LC-VCO that achieves a VCO tuning vary of 20G to 29 GHz and 0.23 ps RMS jitter at 28.one hundred twenty five GHz. The transmitter output shows only 50 fs duty-cycle distortion. The transceiver will compensate a forty dB insertion loss backplane channel (excluding package) at a knowledge rate of 25.seventy eight Gb/s with eight channels running simultaneously. It is fabricated in twenty eight nm normal CMOS and analog section consumes solely 295 mW at one V supply with transmitter driver at 1.twenty five V. Such low power consumption and performance are achieved by combination of advanced twenty eight nm process, low power and performance driven receiver and transmitter topologies, widely adopted bandwidth extension techniques, built-in analog calibrations and one common PLL with a transformer based mostly VCO for four transceivers.
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