A System-Level Modeling Methodology for Performance-Driven Component Selection in Multicore Architectures


System complexity, driven by both increasing transistor count and customer need for more and more savvy applications, has increased so dramatically that system design and integration can no longer be an after-thought. With this increasing complexity of the system design, it has become very critical to enhance system design productivity to meet the time-to-market demands and reduce product development cost. Real-time embedded system designers are facing extreme challenges in the underlying architectural design selection. This involves the selection of a programmable, concurrent, heterogeneous multiprocessor architecture platform. Such a multiprocessor-system-on-chip platform has set innovative trends for the real-time systems and system-on-chip designers. The consequences of this trend imply a shift in concern from computation and sequential algorithms to modeling concurrency, synchronization, and communication in every aspect of hardware and software co-design and development. Therefore, there is a need for a high level methodology that can provide a complete system modeling and architecture/component selection platform. The proposed six-step system modeling methodology provides a process for performance driven component selection, to avoid costly iterative system design re-spins, thereby enhancing system design productivity. We demonstrate our methodology by applying it onto a network-on-chip architecture for selecting its components given certain system specification and system-level performance requirements.

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