PROJECT TITLE :
CVNS Synapse Multiplier for Robust Neurochips With On-Chip Learning
Designing low noise-to-signal-ratio (NSR) structures is one in every of the main concerns when implementing hardware-based mostly neural networks. In this paper, a brand new continuous valued range system (CVNS) multiplication algorithm for low-resolution surroundings is proposed with accurate results. Using the proposed CVNS multiplication algorithm, VLSI implementation of a high-resolution mixed-signal CVNS synapse multiplier for neurochips with on-chip learning is realized. The proposed CVNS multiplication algorithm provides structures with lower NSR. Therefore, the proposed CVNS multiplication algorithm will be exploited to style strong CVNS Adaline for neurochips with on-chip learning.
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