PROJECT TITLE :
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance
This paper introduces a 2nd harmonic extraction technique and its implementation in a 46.four–58.one GHz frequency synthesizer. The frequency doubling approach relies on tapping second harmonic signals at the VCO provide and tail nodes and amplifying them to produce a differential output. Since the amplifiers don't load the VCO outputs, the proposed technique will not affect either the tuning vary or the frequency of the VCO. Moreover, a unique noise bypass technique is utilised to make sure that the amplifiers don't degrade the VCO part noise. Thence, the frequency synthesizer achieves twenty two.4p.c tuning range (46.four–fifty eight.one GHz) and section noise below –118 dBc/Hz while consuming 66 mW from a one V offer. The stacked common gate amplifier can conjointly be utilized for voltage regulation, providing a relatively constant FOM performance over a 2X power dissipation range. The synthesizer occupies zero.half dozen mm 1 mm in IBM thirty two nm SOI CMOS.
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