Systems Identification Based On Resampling Periodic Signal Implemented In Fpga

PROJECT TITLE :

Systems Identification Based On Resampling Periodic Signal Implemented In Fpga

ABSTRACT:

This paper proposes a new methodology to obtain the set of input-output knowledge of an open loop system, the same as those utilized in a method of parametric identification using recursive strategies in and out of line and its implementation in an FPGA ESPARTAN 3E. This method is applicable to systems with comparatively long stabilization time and are operating at a high frequency, creating it difficult to inject an excitation signal during normal system operation.

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