New Twin Crossbar Architecture of Binary Memristors for Low-Power Image Recognition With Discrete Cosine Transform


In this paper, we propose a new twin crossbar architecture of binary memristors for low-power image recognition. Within the new twin crossbar, we tend to use two identical memristor arrays rather than using the previous complementary memristor arrays of M+ and M−. Thereby, we have a tendency to will apply the discrete cosine transform (DCT) algorithm to cut back the number of low-resistance state (LRS) cells in the 2 identical M+ arrays. With the reduced number of LRS cells in 2 M+ arrays, the power consumption in the crossbar will be considerably saved compared to the previous complementary crossbar that's not suitable to DCT. When the quantity of discarded coefficients within the DCT matrix is 56.twenty five%, 67.19%, seventy six.fifty six%, and 84.38%, the ability consumption of the new twin crossbar is reduced by 51.7%, 61.3%, sixty nine.nine%, and 77.4%, respectively, compared to the previous complementary one.

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