Time-to-digital convertor based on resolution control


During this paper, a coarse-fine time-to-digital converter (TDC) based on Vernier delay line (VDL) was proposed. A new digital circuit was developed for tree delay line and this method led to high resolution and low power consumption. The TDC core was based mostly on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It additionally took advantage of a VDL used in conjunction with an asynchronous scan-out circuitry. The time interval resolution was equal to the difference of delay between buffer of upper and lower chains. Then, with added extra chain in lower delay line, resolution will be controlled and space and power consumption was reduced. Measurement results of the TDC showed the resolution of 4.5 ps and output dynamic range of thirty two-bit and also the differential non-linearity was invariably less the one least significant bits (1LSB), while the integral non-linearity showed the maximum of one least significant bits. This TDC achieved the consumption of 248.nine μW from 1.2 V provide.

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