PROJECT TITLE :
SOI FinFET nFET-to-pFET Tracking Variability Compact Modeling and Impact on Latch Timing
During this paper, nFET-to-pFET (n-to-p) tracking characteristics in 14-nm silicon-on-insulator (SOI) FinFET technology are studied by technology laptop-aided style-based mostly statistical modeling. Compared with planar SOI high- $k$ metal gate CMOS technologies, 14-nm SOI FinFET technology shows higher n-to-p tracking mainly due to the sturdy influence of correlated Fin geometrical variation, plus reduced uncorrelated variation from an innovative work operate process. The impact of the n-to-p tracking characteristics on setup and hold (guard time) of latch circuits is evaluated by corner and Monte Carlo simulation using compact models. It is found that the guard time is significantly modulated by slow/quick and quick/slow corners in sure conditions and, thus should be thought of in guard time design.
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