Impact of Bias Temperature Instability on Soft Error Susceptibility


In this paper, we tend to address the problem of analyzing the consequences of aging mechanisms on ICs' soft error (SE) susceptibility. In particular, we consider bias temperature instability (BTI), namely negative BTI in pMOS transistors and positive BTI in nMOS transistors that are recognized as the most critical aging mechanisms reducing the reliability of ICs. We tend to show that BTI reduces considerably the critical charge of nodes of combinational circuits during their in-field operation, thus increasing the SE susceptibility of the whole IC. We have a tendency to then propose a time dependent model for SE susceptibility evaluation, enabling the employment of adaptive SE hardening approaches, primarily based on the ICs lifetime.

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