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A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS

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A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS


Silicon-photonics is an emerging technology that can overcome the tradeoffs faced by traditional electrical I/O. Thanks to ballooning development costs for advanced CMOS nodes, but, widespread adoption necessitates seamless photonics integration into mainstream processes, with as few method changes as possible. During this work, we demonstrate a silicon-photonic link with optical devices and electronics integrated on the same chip during a zero.18 µm bulk CMOS memory periphery process. To enable waveguides and optics in method-native polysilicon, we introduce deep-trench isolation, placed underneath to forestall optical mode leakage into the majority silicon substrate, and implant-amorphization to scale back polysilicon loss. A resonant defect-trap photodetector using polysilicon eliminates need for germanium integration and completes the totally polysilicon-based mostly photonics platform. Transceiver circuits exploit photonic device integration, achieving 350 fJ/b transmit and seventy one µA pp BER = ten -12 receiver sensitivity at 5 Gb/s. We show high fabrication uniformity and high-Q resonators, enabling dense wavelength-division multiplexing with nine-wavelength 45 Gb/s transmit/receive information-rates per waveguide/fiber. To combat perturbations to variation- and thermally-sensitive resonant devices, we tend to demonstrate an on-chip thermal tuning feedback loop that locks the resonance to the laser wavelength. A five m optical chip-to-chip link achieves five Gb/s whereas consuming three pJ/b and twelve pJ/bit of circuit and optical energy, respectively.

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A Monolithically-Integrated Chip-to-Chip Optical Link in Bulk CMOS - 4.8 out of 5 based on 83 votes

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