PROJECT TITLE :
An Analytical Metal Resistance Model and Its Application for Sub-22-nm Metal-Gate CMOS
Gate resistance, middle of line resistance, and back finish of line resistance in trendy metal-gate CMOS increase drastically as the scale of the gates, interconnects and vias scale down close to or below the majority electron mean free methods (MFPs) of the metal materials. These resistances, especially the gate resistance, impose more and more important RC delay to CMOS circuits and become significant issues in sub-22-nm CMOS. In order to optimize the metal-gate materials and structures for low resistance, correct metal resistance model is required. During this letter, we propose an analytical metal resistance model applicable for metal wires and films even with sub-MFP sizes. Our model includes scattering effects from surfaces, interfaces, and grain boundaries, and has been successfully verified on $W$ metal gates with the feature sizes starting from 20 to seventy nm.
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