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1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor

1 1 1 1 1 Rating 4.80 (49 Votes)

PROJECT TITLE :

1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor

ABSTRACT:

We present a resonant adiabatic mixed-signal 128 × 256 array processor that achieves the energy efficiency of 1.1 TMACS (1012 multiply accumulates per second) per mW of power operating from a 1.6 V DC supply. The 1.9 μm × 9 μm 3T NMOS unit cell with a single-wire pitch multiplexed bit/compute line provides charge-conserving 1b-1b multiplication and single-node charge-domain analog accumulation. A stochastic data modulation scheme minimizes on-chip capacitance variability maintaining sinusoidal clock oscillations near resonance.


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1.1 TMACS/mW Fine-Grained Stochastic Resonant Charge-Recycling Array Processor - 4.8 out of 5 based on 49 votes

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