Algorithm and Architecture for a Low-Power Content-Addressable Memory Based on Sparse Clustered Networks


We propose a low-power content-addressable memory (CAM) employing a replacement algorithm for associativity between the input tag and therefore the corresponding address of the output knowledge. The proposed design is based on a recently developed sparse clustered network using binary connections that on-average eliminates most of the parallel comparisons performed throughout a probe. Therefore, the dynamic energy consumption of the proposed style is considerably lower compared with that of a typical low-power CAM style. Given an input tag, the proposed architecture computes a few prospects for the placement of the matched tag and performs the comparisons on them to locate a single valid match. TSMC sixty five-nm CMOS technology was used for simulation functions. Following a choice of style parameters, such as the number of CAM entries, the energy consumption and therefore the search delay of the proposed style are 8percent, and 26% of that of the standard NAND architecture, respectively, with a tenp.c space overhead. A design methodology primarily based on the silicon space and power budgets, and performance requirements is mentioned.

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