PROJECT TITLE :
Soft error rate estimation of combinational circuits based on vulnerability analysis
Nanometer integrated circuits are getting increasingly susceptible to soft errors and making the soft error rate (SER) estimation an important challenge. In this study, a unique approach is proposed for SER estimation of combinational circuits based mostly on vulnerability analysis. The authors introduce an idea referred to as probabilistic vulnerability window (PVW) which is an inference of necessary conditions for one event transient (SET) to cause observable errors within the circuit. A proposed computational framework calculates PVWs for all circuit gates during a backward-traversing algorithm enabling the circuit designers for an correct and economical SER estimation. Experimental results show that the proposed approach is 2× faster than the traditional SER estimation methods and keep its efficiency when it's applied for estimating the SER considering various different SET widths whereas runtime of ancient estimation methods increases in such cases. Also, results verify the accuracy (average distinction of 0.02) and speedup (concerning four orders of magnitude) of the proposed methodology compared with the Monte Carlo-primarily based fault injection simulation on ISCAS'85 benchmark circuits.
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