PROJECT TITLE :
Refactored Design of I/O Architecture for Flash Storage
Flash storage devices behave quite differently from hard disk drives (HDDs); a page on flash has to be erased before it will be rewritten, and therefore the erasure has got to be performed on a block which consists of a giant range of contiguous pages. It's conjointly necessary to distribute writes evenly among flash blocks to avoid premature wearing. To achieve interoperability with existing block I/O subsystems for HDDs, NAND flash devices use an intermediate software layer, known as the flash translation layer (FTL), that hides these differences. Unfortunately, FTL implementations need powerful processors with a large amount of DRAM in flash controllers and also incur many unnecessary I/O operations which degrade flash storage performance and lifetime. During this paper, we have a tendency to gift a refactored style of I/O architecture for flash storage that dramatically will increase storage performance and lifetime while decreasing the cost of the flash controller. As compared with page-level FTL, our preliminary experiments show a discount of nineteen % in I/O operations, improvement of I/O performance by nine % and storage lifetime by 36 p.c. Yet, our theme uses only 1 128 DRAM memory within the flash controller.
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