Two-Step Write Scheme for Reducing Sneak-Path Leakage in Complementary Memristor Array


In this paper, a new two-step write scheme is proposed to minimize sneak-path leakage in complementary memristor (CM) array, where no selection device is needed. When R $_{rm RESET}$/R $_{rm SET}$ = 100, the new two-step write scheme can increase the array size of CMs 10 times larger than the conventional write. If R $_{rm RESET}$/R $_{rm SET}$ is increased to 500, we can increase the passive array size up to 1000 × 1000 with maintaining the read sensing margin lager than 10% of V$_{rm DD}$. The two-step write scheme will be very essential in realizing passive cross-point array without any selection device that is known to be the ideal architecture for future 3-D memories.

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