PROJECT TITLE :
Electrical Properties of Silicon Nanowire Fabricated by Patterning and Oxidation Process
We are reporting electrical properties of Si nanowire field-effect transistors with a Schottky barrier formed at the electrodes. The channel widths are varied using a top-down process of electron-beam patterning followed by surface oxidation from a few micrometers to the sub-10-nm level. The field-effect mobility increases gradually with decreasing channel width to 20 nm. On the other hand, the mobility decreases drastically when the channel width is smaller than 20 nm. The mobility enhancement is attributed to the stress build up during the oxidation of nanowire, while the drastic mobility degradation observed below a 20-nm linewidth is attributed to the surface scattering of electrons caused by the high surface/volume ratio of nanowire. The highest mobility value was obtained at a 20-nm linewidth with a value of ∼1270 cm$^2$/Vs.
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