PROJECT TITLE :
Ensuring Cache Reliability and Energy Scaling at Near-Threshold Voltage With Macho
Nanoscale process variations in conventional SRAM cells are known to limit voltage scaling in microprocessor caches. Recently, a range of novel cache architectures have been proposed which substitute faulty words of one cache line with healthy words of others, to tolerate these failures at low voltages. These schemes depend upon the fault maps to spot faulty words, inevitably increasing the chip space. Besides, the relationship between word sizes and the cache failure rates is not well studied in these works. During this paper, we analyze the word substitution schemes by using Fault Tree Model and Collision Graph Model. A unique cache architecture (Macho) is then proposed based mostly on this model. Macho is dynamically reconfigurable and is locally optimized (tailored to native fault density) using two algorithms: 1) a graph coloring algorithm for moderate fault densities and a couple of) a bipartite matching algorithm to support high fault densities. An adaptive matching algorithm allows on-demand reconfiguration of Macho to concentrate obtainable resources on cache working sets. Hence, voltage scaling all the way down to four hundred mV is possible, tolerating bit failure rates reaching 1 p.c (one failure in each a hundred cells). This near-threshold voltage (NTV) operation achieves forty four p.c energy reduction in our simulated system (CPU DRAM models) with a 1 MB L2 cache.
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