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CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing

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CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing


We tend to have designed, fabricated, and measured the performance of a linear and space-efficient implementation of the compressive sensing (CS) method in CMOS image sensors. The employment of an active pixel sensor (APS) with an integrator and in-pixel current switches are exploited to develop a compact implementation of CS encoding in analog domain. The intrinsic linearity of APS with integrator circuit guarantees the linearity of the CS encoding structure. The CS measurement method is performed for various blocks of the imager separately. This block-primarily based implementation provides individual access to all the pixels from outside the array, resulting in a very scalable style with relatively high fill-factor using only 2 transistors in every pixel. The CS-CMOS image sensor is designed and fabricated in one hundred thirty-nm technology for , , and arrays. The linearity of the extracted measurement is confirmed by the experimental results from and blocks. Additionally, the block readout scheme and therefore the scalability of the design is examined by fabricating a larger array of blocks.

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CMOS Image Sensor With Area-Efficient Block-Based Compressive Sensing - 4.9 out of 5 based on 18 votes

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