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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic

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Aging-Aware Reliable Multiplier Design With Adaptive Hold Logic


Digital multipliers are among the foremost crucial arithmetic purposeful units. The performance of those systems depends on the throughput of the multiplier. Meanwhile, the negative bias temperature instability impact happens when a pMOS transistor is below negative bias $(V_rm gs=-V_rm dd)$ , increasing the brink voltage of the pMOS transistor, and reducing multiplier speed. A similar phenomenon, positive bias temperature instability, occurs when an nMOS transistor is below positive bias. Each effects degrade transistor speed, and in the long term, the system might fail thanks to timing violations. So, it is vital to design reliable high-performance multipliers. During this paper, we propose an aging-aware multiplier design with a completely unique adaptive hold logic (AHL) circuit. The multiplier is ready to produce higher throughput through the variable latency and will adjust the AHL circuit to mitigate performance degradation that is thanks to the aging impact. Moreover, the proposed architecture will be applied to a column- or row-bypassing multiplier. The experimental results show that our proposed design with sixteen $,times,$ sixteen and 32 $,times,$ 32 column-bypassing multipliers will attain up to 62.88p.c and 76.twenty eightpercent performance improvement, respectively, compared with 16 $,times,$ 16 and thirty two $,times,$ thirty two fixed-latency column-bypassing multipliers. Furthermore, our proposed design with sixteen $,times,$ 16 and thirty two $,times,$ 32 row-bypassing multipliers will a- hieve up to 80.17p.c and 69.fortypercent performance improvement as compared with sixteen $,times,$ sixteen and 32 $,times,$ thirty two mounted-latency row-bypassing multipliers.

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