A Phase-Interpolation and Quadrature-Generation Method Using Parametric Energy Transfer in CMOS


This work focuses on generation of quadrature clocks with high phase accuracy and low noise, whereas reducing space and power consumption. The planning objective is to create these quadrature oscillators suitable for applications in power- and area-constrained SOCs. We have a tendency to demonstrate in this work quadrature clock generation using parametric capacitance modulation in CMOS technology. We gift a quadrature-generation methodology that's primarily based on parametric energy transfer to an LC resonator. The part-sensitive nature of parametric pumping is employed to come up with a symptom in quadrature with an incoming clock signal. The planning additionally provides the potential of part interpolation regarding quadrature, that is helpful in several applications. The detailed system implementation is demonstrated and experimentally verified through a prototype in sixty five nm CMOS.

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