Fast and Memory-Efficient Routing Algorithms for Field Programmable Gate Arrays With Sparse Intracluster Routing Crossbars


Field programmable gate array (FPGA) routing is one in all the foremost time consuming steps in a very typical laptop-aided style flow. The matter itself is similar to the NP-complete problem of computing a collection of disjoint ways in an exceedingly graph. The routing resource graph (RRG) that represents an FPGA routing network is necessarily large, and becomes even larger when modeling fashionable FPGAs that integrate sparse intracluster routing crossbars. This paper introduces two scalable heuristics that reduce the runtime and memory footprint of FPGA routing: one) selective RRG expansion (SERRGE), which employs an application-specific memory manager that stores the RRG during a compressed type, and dynamically decompresses it because the router proceeds and a pair of) partial prerouting (PPR) locally routes all nets within each logic cluster, followed by a international routing stage to finish the routes. PPR and SERRGE converge faster than a traditional router using a absolutely expanded RRG. PPR runs faster and uses less memory than SERRGE, while SERRGE yields the best clock frequencies among the three.

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