MTech Projects
  • HOME
  • MTECH PROJECTS
    • COMPUTER SCIENCE
      • MTech Python Projects
        • Machine Learning Projects
        • Deep Learning Projects
        • Blockchain Projects
        • django Projects
      • MTech Java Projects
        • Cloud Computing Projects
        • Data Mining Projects
        • Mobile Computing Projects
        • Networking Projects
      • MTech NS2 Projects
        • Wireless Communication Projects
        • Vehicular Technology Projects
      • MTech Hadoop Projects
      • MTech Android Projects
    • ELECTRONICS
      • MTech DSP Projects
      • MTech DIP Projects
      • MTech VLSI Projects
      • MTech Communication Projects
    • ELECTRICAL
      • MTech Power Systems Projects
      • MTech Power Electronics Projects
      • MTech Control Systems Projects
    • OTHER
      • Chemical Projects
      • Mechanical Projects
      • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Contact Us

  • Street Number 4, Jawahar Nagar, RTC X Road, Hyderabad 500044
  • +91 9573777164
  • info@mtechprojects.com

Welcome to MTech Projects - Online Projects for MTech Students

  • My Account
  • Careers
  • Downloads
  • Blog
MTech Projects
  • Email Us
  • Phone Number
  • Open Hours
  • HOME
  • MTECH PROJECTS

    MTech Python Projects

    • Machine Learning Projects
    • Deep Learning Projects
    • Blockchain Projects
    • django Projects

    MTECH JAVA PROJECTS

    • Cloud Computing Projects
    • Data Mining Projects
    • Mobile Computing Projects
    • Networking Projects

    MTECH NS2 PROJECTS

    • Wireless Communication Projects
    • Vehicular Technology Projects
    • MTech Hadoop Projects
    • MTech Android Projects

    ELECTRONICS

    • MTech DSP Projects
    • MTech DIP Projects
    • MTech VLSI Projects
    • MTech Communication Projects

    ELECTRICAL

    • MTech Power Systems Projects
    • MTech Power Electronics Projects
    • MTech Control Systems Projects

    OTHER

    • Chemical Projects
    • Mechanical Projects
    • All Other Projects
  • EMBEDDED KITS
    • MTech Embedded Kits
    • BTech Embedded Kits
  • PROJECTS+
  • PUBLISHING
    • Research Publishing
    • Authors Guidelines
    • Publishing Policy
  • CONTACT US

Project Enquiry

  1. You are here:  
  2. Home
  3. IEEE MTECH VLSI ( VHDL/VERILOG ) PROJECTS
  4. A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016
Details
Category: MTECH VLSI ( VHDL/VERILOG ) PROJECTS
By MTech Projects
MTech Projects
27.Mar
Hits: 11

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016

PROJECT TITLE:

A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications - 2016

ABSTRACT:

Transpose type finite-impulse response (FIR) filters are inherently pipelined and support multiple constant multiplications (MCM) technique that ends up in vital saving of computation. However, transpose form configuration does not directly support the block processing in contrast to direct-type configuration. During this project, we tend to explore the chance of realization of block FIR filter in transpose kind configuration for space-delay efficient realization of huge order FIR filters for each fastened and reconfigurable applications. Primarily based on a detailed computational analysis of transpose form configuration of FIR filter, we have a tendency to have derived a flow graph for transpose kind block FIR filter with optimized register complexity. A generalized block formulation is presented for transpose type FIR filter. We tend to have derived a general multiplier-based mostly architecture for the proposed transpose type block filter for reconfigurable applications. A coffee-complexity style using the MCM scheme is additionally presented for the block implementation of fastened FIR filters. The proposed structure involves significantly less area-delay product (ADP) and fewer energy per sample (EPS) than the prevailing block implementation of direct-type structure for medium or giant filter lengths, whereas for the short-length filters, the block implementation of direct-type FIR structure has less ADP and fewer EPS than the proposed structure. Application-specific integrated circuit synthesis result shows that the proposed structure for block size 4 and filter length 64 involves 42percent less ADP and 40% less EPS than the simplest out there FIR filter structure proposed for reconfigurable applications. For the identical filter length and the same block size, the proposed structure involves 13p.c less ADP and twelve.eightp.c less EPS than that of the present direct-form block FIR structure.

Did you like this research project?

To get this research project Guidelines, Training and Code... Click Here

  • An All-Digital Scalable and Reconfigurable Wide-Input Range Stochastic ADC Using Only Standard Cells - 2015
  • Detection of Hardware Trojan in SEA Using Path Delay
  • On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays
  • A High-Performance FIR Filter Architecture forFixed and Reconfigurable Applications - 2016
  • Secrecy Rate Optimizations for a MIMO Secrecy Channel With a Cooperative Jammer - 2015
  • Low-Complexity Low-Latency Architecture for Matching of Data Encoded With Hard Systematic Error-Correcting Codes
  • Design and Analysis of Approximate Compressors for Multiplication - 2015
  • A Low Complexity Multiple Error Correcting Architecture Using Novel Cross Parity Codes Over GF(2m) - 2014
  • High-Performance and High-Yield 5 nm Underlapped FinFET SRAM Design using P-type Access Transistors - 2015
  • A Fault Detection and Tolerance Architecture for Post-Silicon Skew Tuning - 2015
Previous article: An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC - 2015 An Efficient VLSI Architecture of a Reconfigurable Pulse-Shaping FIR Interpolation Filter for Multistandard DUC - 2015 Next article: A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT - 2015 A Combined SDC-SDF Architecture for Normal IO Pipelined Radix-2 FFT - 2015
COMPUTER SCIENCE PROJECTS ELECTRONICS PROJECTS MTech DSP Projects MTech DIP Projects MTech VLSI Projects MTech VHDL Projects MTech Verilog Projects MTech Communication Projects ELECTRICAL PROJECTS EMBEDDED PROJECTS MECHANICAL PROJECTS

sell academic m.tech, btech and be projects online

sell academic m.tech, btech and be projects online

Academic Final Year Projects

QUICK LINKS

  • Python Projects List
  • Java Projects with Source Code in NetBeans
  • Android Projects Download
  • Core Java Projects
  • Simple Python Projects
  • Android Projects with Source Code in Android Studio
  • Segmentation in Image Processing
  • Python Projects with Database
  • Digital Signal Processing pdf
  • Image Processing Using Python
  • VLSI Projects for Final Year ECE
  • Power Electronic Projects
  • Power System Projects
  • VLSI Projects for MTech
  • Power System Projects using Matlab
  • Power Electronics and Drives
SUPPORT
+91 9573777164
9:00am - 6:00pm IST
info@mtechprojects.com

Navigate

  • ABOUT
  • TESTIMONIALS
  • FIND A DEALER
  • CAREERS

CONTACT

  • CONTACT
  • FAQ
  • RESOURCES
  • EMAIL US

Useful links

  • REFUND & RETURN POLICY
  • PRIVACY POLICIES

Support

  • FACEBOOK
  • TWITTER
  • PINTEREST
  • GOOGLE PLUS

Disclaimer : MTech Projects, is not associated or affiliated with IEEE, in any way. The mentioned IEEE Projects here are student projects inspired by ideas from IEEE publications, not projects conducted by or associated with IEEE.

Talk to us?

Copyright © 2026 MTech Projects. All Rights Reserved.