PROJECT TITLE :
Simulation, Analysis, and Verification of Substrate Currents for Layout Optimization of Smart Power ICs
Today circuit failures in Smart Power ICs because of substrate couplings are partially addressed during the circuit style part. The state-of-the-art guidelines for the optimization of parasitic couplings offer mainly qualitative rules, that are tough to implement and to verify throughout the look of a complicated Good Power circuit. These rules are typically based on the physical device simulations or on the empirical results extracted from predefined benchmark structures. In this paper, a novel approach is proposed for designing strong circuits integrating accurate and specific analysis of substrate couplings already into the design flow. First, substrate currents injected by power transistors are discussed to point out the spatial distribution of voltage and currents into the substrate. A collection of guidelines to optimize substrate currents is presented as a summary of the studied check cases. Then, an H-Bridge output driver was implemented during a zero.35- μm HVCMOS technology to investigate substrate currents by each measurements and simulations. Reverse currents were deliberately injected into the chip to activate substrate lateral and vertical parasitic bipolar junction transistors and measured data closely match circuit simulation ends up in each cases.
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