Designing Chip-Level Nanophotonic Interconnection Networks


Technology scaling will soon enable high-performance processors with hundreds of cores integrated onto one die, but the success of such systems might be limited by the corresponding chip-level interconnection networks. There are several recent proposals for nanophotonic interconnection networks that attempt to provide improved performance and energy-potency compared to electrical networks. This paper discusses the approach we have used when planning such networks, and provides a foundation for designing new networks. We have a tendency to begin by briefly reviewing the essential silicon-photonic device technology before outlining style problems and surveying previous nanophotonic network proposals at the architectural level, the microarchitectural level, and also the physical level. In coming up with our own networks, we have a tendency to use an iterative method that moves between these three levels of style to fulfill application needs given our technology constraints. We have a tendency to use our ongoing work on leveraging nanophotonics in an on-chip title-to-tile network, processor-to-main-memory network, and dynamic random-access memory (DRAM) channel to illustrate this style method.

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