PROJECT TITLE :
Fractional-N multiplying delay-locked loop with delay-locked loop-based injection clock generation
A fractional-N multiplying delay-locked loop (MDLL) with delay-locked loop (DLL)-based injection clock generation is presented. By exploiting multiphase output of DLL that delay is locked to the amount of output frequency, the proposed architecture performs a fractional clock multiplication with MDLL, while eliminating deterministic jitter from fractional divider. The proposed MDLL is meant in an exceedingly 0.18 μm CMOS process and achieves 31.25 kHz frequency resolution with one MHz reference frequency. It occupies a lively space of zero.055 mm2, and consumes forty five μW for ten MHz frequency generation, showing energy efficiency figure-of-advantage (FoM) of 4.five μW/MHz.
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