PROJECT TITLE :
Energy-efficient switching method for SAR ADCs with bottom plate sampling
A high energy-efficiency capacitor switching theme for successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The switching methodology, verified on a 10-bit SAR theme that uses bottom plate sampling, achieves a median switching energy and area reduction of 99.32 and 96.fivep.c, respectively, with respect to the traditional answer.
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