Embedding of signatures in reconfigurable scan architecture for authentication of intellectual properties in system-on-chip


Signature-based mostly authentication is employed often to authenticate hardware intellectual property (IP) when it is reused on a plug-and-play system-on-chip. A signature embedded within the functional/test part of a hardware IP can easily be verified because it can be generated and observed as functional/scan output of the hardware IP for a certain input key vector. An existing scan-based approach for embedding signature inserts signature through reordering of scan cells in a very single scan (SS) chain. But, it's not applicable to the recent reconfigurable scan architectures having reduced check application time. We tend to propose a theme for embedding two distinct signatures separately in an exceedingly reconfigurable scan design and verifying those without conflict from the packaged chip by using 2 distinct check modes of the reconfigurable design: namely, scan tree mode and SS mode. The two signatures might include one from logic IP source and the other from physical IP supply. The overhead in both routing and power has been minimised in our theme. Experimental results on design overhead and robustness for ISCAS89 benchmarks are terribly encouraging.

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