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5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory

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PROJECT TITLE :

5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory

ABSTRACT:

A replacement low-power, fast-locking, all-digital delay-locked loop (DLL) that uses a disposable time-to-digital converter (TDC) is presented for future memory systems beyond double data rate 4. To attain quick locking and high-frequency operation, the proposed DLL utilises a brand new hybrid (TDC + binary + sequential) search algorithm that ends up in a fast locking time of 11 clock cycles without the false lock and harmonic lock issues. By minimising the intrinsic delay of the digital delay line, the proposed DLL achieves an operating frequency vary of 1.5–5.0 GHz which is higher than that of the current state-of-the-art all-digital DLLs. The DLL is fabricated in a 65 nm CMOS method and it achieves a peak-to-peak (p–p) output clock jitter of 14 ps (with a p–p input clock jitter of 8 ps) at 5 GHz. The DLL consumes half-dozen.nine mW at 1 V and occupies an energetic space of 0.025 mm2.


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5 GHz all-digital delay-locked loop for future memory systems beyond double data rate 4 synchronous dynamic random access memory - 4.9 out of 5 based on 24 votes

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