Controlled delay-through dynamic logic: leakage-tolerant high-speed dynamic logic


A replacement model for dynamic logic is proposed with low power consumption and leakage while not the degradation of speed. This logic works perfectly with cascaded and differential style while not inverters. Controlled delay-through dynamic logic (CDTDL) is relatively faster than alternative dynamic logics because of the parallel-sort configuration with clock and inputs. CDTDL-primarily based circuits will perform higher in high-frequency operations due to lower propagation delay and dynamic power consumption at the price of area. The proposed technique will avoid the prospect of leakage current with the help of a control block and a delayed clock mechanism. The simulation results show that the new dynamic logic using 180 nm technology yields a minimum forty improvement in power delay product compared with its predecessors like typical domino and current comparison-primarily based domino for standard circuits.

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